Static, random-access memories (SRAMs) employ a number of cells, each for storing a single binary bit of information. Typical, prior art type, SRAM cell structures include what is commonly referred to as a four-transistor, two-resistor (4T-2R) SRAM cell and what is commonly referred to as a six-transistor (6T) SRAM cell. A prior art type (4T-2R) SRAM cell is illustrated in (prior art) FIG. 1 of the drawing, generally designated by the number 100. SRAM cell 100 is shown to include four, N-channel, transistors, which are respectively designated 110, 112, 114, and 116, and two (load) resistors, which are respectively designated 120 and 122 and which have a relatively high resistance. Transistor 110 is configured as a transfer transistor with the transistor gate connected to an (active high) word (control) line (WL), which is designated 130 and which is driven by an address decoder 132. The channel of transistor 110 is connected between a node 134 and an (active high) bit (input/output) line (BL) 136. Transistor 112 is configured as a pull-down transistor with the transistor gate connected to a node 140 and with the transistor channel connected between node 134 and a line 142, which is connected to a circuit ground potential (Vss). Also, configured as a pull-down transistor, the gate of transistor 114 is connected to node 134; and, the channel of the transistor is connected between node 140 and circuit ground potential line 142. Transistor 116 is, also, configured as a transfer transistor with the transistor gate connected to word (control) line (WL) 130 and with the transistor channel connected between node 140 and an (active low) bit (input/output) line (/BL) 144. Finally, resistors 120 and 122 are configured as a pull-up resistors, resistor 120 being connected between node 134 and a line 146, which is connected to a power-supply potential (Vcc), and resistor 122 being connected between node 140 and power-supply-potential line 146.
Illustrated in (prior art) FIG. 2, generally designated by the number 200, is a prior art type, six transistor (6T) SRAM cell. The six transistor (6T) SRAM cell (200) differs from the four transistor, two resistor (4T-2R) SRAM cell (100) (illustrated in FIG. 1) in that the (6T) SRAM cell (200) includes two, P-channel, (load) transistors, respectively designated 220 and 222, in place of the resistors (120 and 122) of the (4T-2R) SRAM cell (100). The transistor replacing resistor 120 is configured with the transistor gate connected to a node 140' and with the transistor channel connected between a power-supply-potential line 146' and a node 134'. Similarly, the transistor replacing resistor 122 is configured with the transistor gate connected to node 134' and with the transistor channel connected between power-supply-potential line 146' and node 140'.
Operationally, when a binary bit of information is being stored in SRAM cell 100 (illustrated in FIG. 1 or SRAM cell 200 illustrated in FIG. 2), address decoder 132 develops a high-logic-level potential on (active high) word (control) line (WL) 130 to select the cell. In addition, a strong, complementary, signal is externally developed on (active high) bit (input/output) line (BL) 136 and (active low) bit (input/output) line (/BL) 144, as is appropriate to represent the state of the binary bit of information being stored in SRAM cell 100 (or SRAM cell 200).
When a binary bit of information is being retrieved from SRAM cell 100 (illustrated in FIG. 1 or SRAM cell 200 illustrated in FIG. 2), address decoder 132, again, develops a high-logic-level potential on (active high) word (control) line (WL) 130 to select the cell. In this case, however, no potential is externally forced on either (active high) bit (input/output) line (BL) 136 or (active low) bit (input/output) line (/BL) 144. Rather, SRAM cell 100 (or SRAM cell 200) is allowed to develop on (active high) bit (input/output) line (BL) 136 and (active low) bit (input/output) line (/BL) 144 potentials, the levels of which are appropriate to represent the state of the binary bit of information currently stored in SRAM cell 100 (or SRAM cell 200).
Common practice is to employ resistors (120 and 122) of relatively high resistance for the load resistors of the four-transistor, two-resistor (4T-2R) SRAM cell (shown in FIG. 1) and to employ transistors (220 and 222) of relatively small size for the load transistors of the the six transistor (6T) SRAM cell (shown in FIG. 2). As a consequence, they (the load resistors and transistors) are not able to effectively pull-up the level of potentials developed on the bit lines. To pull-up the level of the potentials developed on the bit lines (for fast write recovery) and to prevent a low bit line potential level from disturbing the state of the binary bit of information stored in a cell, common practice is to pull-up the level of the potentials on the bit lines externally, statically pre-charging the lines. For this purpose, common practice is to employ a pair of bit-line pull-up resistors, each connected between a power-supply potential (Vcc) and the respective one of the bit lines. Also, to equalize the level of the potentials developed on the bit lines and to limit their swing, common practice is to employ a transistor configured with the transistor channel connected between the bit lines. Unfortunately, contention occurs between the active one of the SRAM cell pull-down transistors (112 or 114) and the corresponding bit-line pull-up resistor. In addition, the limited, differential, bit line potentials (of a few hundred millivolts) must be amplified (to CMOS) potential levels. For this purpose, a sense amplifier which has a relatively high gain and dissipates a relatively large amount of power is employed.
Other prior-art implementations employ pre-charge circuits of the type which is illustrated in (prior art) FIG. 3, generally designated by the number 300. Pre-charge circuit 300 is shown to include three, P-channel, transistors, which are respectively designated 310, 312, and 314. Transistor 310 is configured with the transistor gate connected to an (active low) pre-charge (control) line, which is designated 320 and which is driven by an address change detection circuit 322. The channel of transistor 310 is connected between an (active high) bit (input/output) line (BL) 136" and a line 324, which is connected to a power-supply potential (Vcc). Transistor 312 is configured with the transistor gate connected to pre-charge line 320 and with the transistor channel connected between bit line (BL) 136" and an (active low) bit (input/output) line (/BL) 144". Transistor 314 is configured with the transistor gate connected to pre-charge line 320 and with the transistor channel connected between bit line (/BL) 144" and power-supply-potential line 324.
Operationally, when a low-logic-level potential is momentarily developed on (active low) pre-charge (control) line 320, (just before a binary bit of information is to be retrieved from a SRAM cell) transistors 310 and 314 pull-up the level of the potentials developed on (active high) bit (input/output) line (BL) 136" and (active low) bit (input/output) line (/BL) 144". Transistor 312 pulls-up the lower level potential, equalizing the level of the potentials developed on bit lines 136" and 144", to develop a uniform (matching) high-potential level thereon.
A prior art type address-change-detection circuit is shown in FIG. 9 of the article by Donoghue et al entitled "ROM Using A Four-State Cell Approach" published on page 601 of the IEEE Journal Of Solid State Circuits Vol. SC-20 No. 2. The above mentioned, address-change-detection circuit, which is illustrated, herein, in (prior art) FIG. 4, generally designated by the number 322', employs a number of, similar, address-change-detectors, one for each (binary) address signals. One such address-change-detector is illustrated, herein, in FIG. 4, generally designated by the number 410. Address-change-detector 410 is shown to have a pair of, similar, waveform conditioners, generally designated designated 420 and 422, respectively, and a two-input NAND gate, generally designated 426. Waveform conditioner 420 has an input connected to a line 430 to receive the (binary) address signal and an output coupled by a line 432 to one of the two inputs on NAND gate 426. Waveform conditioner 422 has an input connected to a line 434 to receive the compliment (inverse) of the (binary) address signal developed on line 430 and an output coupled by a line 436 to the other one of the two inputs on NAND gate 426. The output of NAND gate 426 is connected to a "common bus" line 438.
Typical of the waveform conditioners, waveform conditioner 420 includes a P-channel transistor, designated 440, and a pair of N-channel transistors, respectively designated 442 and 444. Transistors 440, 442, and 444 are connected in a totem-pole configuration in which the channel of transistor 440 is connected, one end to receive a power-supply potential (Vcc) and the other end to the channel of transistor 442; the channel of transistor 442 is connected between the channel of transistor 440 and the channel of transistor 444; and the channel of transistor 444 is connected, one end to the channel of transistor 442 and the other end to receive a circuit-ground potential (Vss). The gate of transistor 442 is connected to receive a power-supply potential (Vcc). The gates of transistors 440 and 444 are connected to the waveform conditioner (420) input (line 430); and, the waveform conditioner (420) output (line 432) is connected to the juncture of the channels of transistors 440 and 442.
It is indicated in the article that the width of the channel of the middle transistor (442) is much smaller than the length of the channel of the transistor. As a consequence, the middle transistor (442) functions as a resistor, limiting the rate at which the lower transistor (444) can pull-down the level of a potential developed at the waveform conditioner (420) output. Thus, each of the waveform conditioners (including waveform conditioner 420) functions as an inverter having a relatively fast rise time and a relatively slow fall time. In other words, waveform conditioner 420 develops at waveform conditioner output (line 432) a waveform having a relatively fast rise time and a relatively slow fall time. Responsive to the change in state of a pair of (binary) address signals (such as those developed on lines 430 and 434), one of the respective pair of waveform conditioners (420 or 422) changes the state (pulls-down) the level of the potential developed at the waveform conditioner output a period of time after the other one of the pair of waveform conditioners (420 or 422) changes the state (pulls-up) the level of the potential developed at the waveform conditioner output. Responsive thereto, the corresponding NAND gate (438) develops on "common bus" line 438 a potential, the level of which goes low for a period of time. (In other words, each of the waveform conditioners functions much as an exclusive-NOR gate driven, one input directly by a signal and the other input by the signal delayed, as by a pair of cascade connected inverters.)
Although not show in either the above mentioned article or herein, for proper operation, it is believed that address-change-detection circuit 322' requires a number of TTL-to-CMOS level converters, one between each waveform conditioner input and the corresponding (binary) address line.
The various address-change-detectors (of the above-mentioned address-change-detection circuit 322') are connected in a "wired-AND" configuration. Specifically, the output of NAND gate 426 (of address-change detector 410) is connected to "common bus" line 438, as is the output of each of the other NAND gates (each of the respective one of the other address-change-detection circuit 322' address-change detectors), as represented by a NAND gate 440.
In addition, address-change-detection circuit 322' employs a pull-up circuit that includes an N-channel transistor 450 and a P-channel transistor 452. To pull-up the level of the potential developed on a line 456, transistor 452 is configured with the transistor gate connected to receive a circuit ground potential (Vss) and with the transistor channel connected, one end to receive a power-supply potential (Vcc) and the other end to line 456. Transistor 450 is configured with the transistor gate connected to receive a power-supply potential (Vcc) and with the transistor channel connected between lines 438 and 456, to limit the level of the potential developed on line 438 to a potential level of Vcc minus the Vt of the transistor.
Finally, address-change-detection circuit 322' employs a pair of inverters, 460 and 462, respectively. Inverters 460 and 462 are connected in cascade (series) between line 456 and an output line 466, upon which address-change-detection circuit 322' develops an (active low) pre-charge (control) line pulse.
It is important to note that the above-mentioned, address-change-detection circuit (322') is an "open-loop" circuit. As a consequence, it is very difficult to establish the width of the pre-charge pulse developed by address-change-detection circuit 322' on line 466. Specifically, the width of the line 466 pre-charge pulse is established by various combinations of the fall times of the various waveform conditioners. The fall times of the various waveform conditioners (including waveform conditioner 420) is established by the middle transistor (transistor 442 for waveform conditioner 420), the characteristics of which are process, temperature, and power-supply potential (Vcc) dependent.
In addition, the width of the line 466 pre-charge pulse is dependent on the number of (binary) address signals (including the signal developed on line 430) which change state. This is because transistors 450 and 452 source a predetermined current level into line 438. Each of the NAND gates (including NAND gates 426 and 440) sink a predetermined current level from line 438. Thus, the fall time of the potential developed on line 438 is dependent on the number of (binary) address signals which change state.
Further, the width of the line 466 pre-charge pulse is dependent on the skew of the timing of the various (binary) address signals.
Unfortunately, static, random-access memories (SRAMs) employing the above mentioned address-change-detection circuit (322') must allow for the worst case width of the line 466 pre-charge pulse. As a consequence, static, random-access memories (SRAMs) employing the above mentioned address-change-detection circuit (322') are relatively slow (have a relatively long access time).